Controlling distributed power stages responsive to the activity level of functions in an integrated circuit

ABSTRACT

A method includes obtaining an activity level for each of a plurality of functions of an integrated circuit, wherein each function has a different physical location on the integrated circuit. The method further includes dynamically adjusting an amount of current supplied to the integrated circuit by each of a plurality of power stages of a DC voltage regulator to meet the current requirements of the plurality of functions and to control power losses between the power stages and the functions, wherein each power stage has a different physical location along a perimeter of the integrated circuit.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.14/330,687 filed on Jul. 14, 2014, which application is incorporated byreference herein.

BACKGROUND

1. Field of the Invention

The present invention relates to systems and methods for providingdirect current to an integrated circuit.

2. Background of the Related Art

Integrated circuits are often installed on a printed circuit board thatprovides mechanical support, electrical power, and communicationchannels to other components on the printed circuit board. The printedcircuit board may be formed with multiple laminated layers including anelectrically conductive power plane and an electrically conductiveground plane. The power and ground planes provide a means for electricalpower distribution across the printed circuit board. Various components,such as an integrated circuit, may be coupled to the power and groundplanes in order to receive electrical power. A component may be coupledto the power and ground planes by plated through holes referred to asvias.

While a computer may be plugged into an alternating current (AC)electrical outlet or cable, a power supply converts the alternatingcurrent to direct current for use by the integrated circuits and othercomponents within the computer. Direct current (DC) is provided to thepower plane for distribution to the various components. Furthermore,various components installed on the printed circuit board may requiredifferent DC voltages, such that it is necessary to provide DC-DCvoltage regulators that step down the DC voltage to the appropriatelevel.

BRIEF SUMMARY

One embodiment of the present invention provides a method, comprisingobtaining an activity level for each of a plurality of functions of anintegrated circuit, wherein each function has a different physicallocation on the integrated circuit. The method further comprisesdynamically adjusting an amount of current supplied to the integratedcircuit by each of a plurality of power stages of a DC voltage regulatorto meet the current requirements of the plurality of functions and tocontrol power losses between the power stages and the functions, whereineach power stage has a different physical location along a perimeter ofthe integrated circuit.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a schematic plan view of a system including a DC voltageregulator having power stages located around a perimeter of anintegrated circuit.

FIG. 2 is a diagram of the system illustrating current conductions pathsfrom each of the power stages to an active function of the integratedcircuit.

FIG. 3 is a diagram of the system illustrating power losses whenproviding power to the active function from two power stages that are onthe opposite side of the integrated circuit from the active function.

FIG. 4 is a diagram of the system illustrating power losses whenproviding power to the active function from two power stages on opposingsides of the integrated circuit function.

FIG. 5 is a diagram of the system illustrating power losses whenproviding power to the active function from the power stage that is thenearest to active function.

FIG. 6 is a flowchart of a method according to one embodiment of thepresent invention.

DETAILED DESCRIPTION

One embodiment of the present invention provides a method, comprisingobtaining an activity level for each of a plurality of functions of anintegrated circuit, wherein each function has a different physicallocation on the integrated circuit. The method further comprisesdynamically adjusting an amount of current supplied to the integratedcircuit by each of a plurality of power stages of a DC voltage regulatorto meet the current requirements of the plurality of functions and tocontrol power losses between the power stages and the functions, whereineach power stage has a different physical location along a perimeter ofthe integrated circuit.

The plurality of functions of the integrated circuit may include varioussub-circuits or sections that facilitate different operations. Thefunctions may include, for example, processor cores, unique circuitblocks, different logic domains, or memories. In one embodiment, theintegrated circuit include multiple processor cores, such as fourprocessor cores physically located in separate quadrants of theintegrated circuit.

Embodiments of the present invention control power losses between eachpower stage and each function by adjusting an amount of current suppliedby each of the power stages. Preferably, the amount of current suppliedby each power stage is dynamically adjusted to reduce power lossesbetween the power stages and the functions relative to an amount ofpower losses that would occur if each power stage provided an equalamount of current. Still further, the amount of current supplied by eachpower stage may be weighted according to the activity level of afunction closest to each power stage. Most preferably, the amount ofcurrent supplied by each power stage may be dynamically adjusted tominimize power losses between the power stages and the functions. Theamount of current to be supplied by each power stage may be determinedusing a power loss equation or by accessing a fixed lookup table thatidentifies an amount of current for each power stage that is appropriatefor a particular activity level of each function.

An optional logic for minimizing the power losses may be performed withknowledge of the resistance of each conduction path between a powerstage and a function, knowledge of the range of possible currentconsumption from each and every function, and knowledge of the range ofpossible current delivery from each and every power stage (Ex. 0 A tomaximum load or power stage acceptable current limit). Then the logiccan calculate the total power loss of the system considering eachpossible combination of power stage and function, and, for a given loadoperating point, select the power stage current weighting which yieldsthe lowest total calculated power loss value for that load operatingpoint.

The different physical locations of the power stages along the perimeterof the integrated circuit provide a variety of path lengths to each ofthe functions. Providing more current through a shorter path lengthbetween a power stage and a function can reduce the overall power lossesassociated with supplying power to the function. In one embodiment, theintegrated circuit may be rectangular and the plurality of power stagesmay be located on at least two opposing sides of the integrated circuit.For example, the plurality of functions may include at least fourfunctions and the plurality of power stages may include at least fourpower stages. Preferably, at least one of the power stages will bedirectly adjacent each one of the functions, since this provides a veryshort conductive path length. In another example, the plurality of powerstages may include six power stages distributed around the perimeter ofthe integrated circuit, with two power stages located on each of threesides of the integrated circuit.

However, the distance between a power stage and a function is notnecessarily the sole determiner of resistance. For example, a firstconduction path between a first power stage and a first function couldbe short but narrow, while a second conduction path between a secondpower stage and a second function could be long but wide and thus nomore resistive than the short path. Also, the total resistance betweeneach power stage and each function may, for example, be influenced bysolder joints, copper thickness, via count, IC power distributioncharacteristics and other characteristics.

While the activity level of each function may be obtained periodicallyor upon occurrence of some event, the activity level of each function ispreferably updated continuously during operation of the integratedcircuit. In a preferred system, an internal controller of the integratedcircuit communicates the activity level of each function to a regulatorcontroller over a control line or bus. Accordingly, the regulatorcontroller may control each of the power stages, such as by dynamicallycontrolling the amount of current provided by each power stage inresponse to the updated activity level for each function.

Power losses between each power stage and each function may becalculated as the sum of the power loss between each power stage andeach function, where the power loss is a function of the square of theamount of current multiplied by the electrical resistance in aconduction path from the power stage to the function. Furthermore, theelectrical resistance in the conduction path may be determined as afunction of electrical resistivity of the particular conduction path anda path length of the particular conduction path. The electricalresistivity of the conduction path is a property of the conductivematerial and geometry, which is typically a thin plane of copper.Accordingly, the system may store a known path length or electricalresistance for each possible pairing of one of the functions and one ofthe power stages. Then, the system may determine an amount of current tobe supplied by one or more of the power stages in order to reduce,minimize or otherwise control the power losses associated with supplyingthe power requirements of the integrated circuit.

For the limited purpose of providing a specific example, the pluralityof functions of an integrated circuit may include a first functionhaving an activity level that is greater than an activity level of theother functions. Furthermore, the plurality of power stages may includea first power stage that is closest to the first function. An amount ofcurrent provided to the integrated circuit by each of a plurality ofpower stages of a DC voltage regulator may be dynamically adjusted in amanner that causes the first power stage to supply a greater than equalportion of the amount of current provided to the integrated circuit.

Various embodiments of the invention may measure or identify an activitylevel of a function of the integrated circuit in different ways andusing different quantitative or qualitative measures. For example, theactivity level may be measured by an instruction counter, or identifiedby a task size or a processor sleep state. Still further, a futureactivity level of a function may be determined by analyzing a queue ofpending workload.

In one option, each power stage supplies electrical current to a powerplane and each function is electrically connected between the powerplane and a ground plane. Accordingly, the power losses between thepower stages and the functions occur in the power plane and the groundplane. The power losses in the power and ground planes may be calculatedas the sum of the power losses between each power stage and eachfunction, wherein each power loss is a function of the square of theamount of current multiplied by the electrical resistance in a currentloop from the power stage to the function through the power plane andfrom the function to the power stage through the ground plane.

Another embodiment of the present invention provides a computer programproduct comprising a computer readable storage medium having programinstructions embodied therewith, the program instructions executable bya processor to cause the processor to perform a method. The methodcomprises obtaining an activity level for each of a plurality offunctions of an integrated circuit, wherein each function has adifferent physical location on the integrated circuit. The methodfurther comprises dynamically adjusting an amount of current supplied tothe integrated circuit by each of a plurality of power stages of a DCvoltage regulator to meet the current requirements of the plurality offunctions and to control power losses between each power stage and eachfunction, wherein each power stage has a different physical locationalong a perimeter of the integrated circuit.

The foregoing computer program products may further include computerreadable program code for implementing or initiating any one or moreaspects of the methods described herein. Accordingly, a separatedescription of the methods will not be duplicated in the context of acomputer program product.

FIG. 1 is a schematic plan view of a system 10 including an integratedcircuit 20 and a DC voltage regulator 30. The integrated circuit 20includes four functions 22A-D (Function A, Function B, Function C, andFunction D), such as processor cores, located in separate quadrants ofthe integrated circuit, and an internal controller 24 (IC Controller).The integrated circuit 20 is installed on a printed circuit board (notshown) that includes a power plane 12. For any given integrated circuit,the location of each function on the integrated circuit is fixed andthose locations are published by the integrated circuit manufacturer.Accordingly, the regulator controller 38 may identify the physicallocation of each function.

The DC voltage regulator 30 includes a regulator controller 38 and sixpower converter stages 31-36, such as synchronous buck power stages,located around a perimeter of the integrated circuit 20. In theimplementation shown, the integrated circuit 20 is rectangular and thereare two regulators located along each of three sides of the rectangularintegrated circuit. Each of the six power stages 31-36 supplieselectrical current to the power plane 12 from a power supply (notshown). The amount of electrical current supplied by any one or more ofthe power stages 31-36 is controlled by the regulator controller 38,which sends a control signal to each power stage 31-36.

For any given integrated circuit 20, the location of each function 22A-Don the integrated circuit is fixed and those locations are availablefrom the integrated circuit manufacturer. Accordingly, the regulatorcontroller 38 may identify the physical location of each function.Similarly, for any printed circuit board, such as a computermotherboard, the location of each power stage is fixed and thoselocations are available from the printed circuit board manufacturer. Theregulator controller 38 may therefore identify the physical location ofeach power stage. Accordingly, the regulator controller 38 may determinethe distance between each power stage and each function. Furthermore, itis preferable to locate the power stages as close as possible to eachfunction so that the conduction path length between a function as anadjacent power stage is minimized.

Where the regulator controller 38 identifies the distance between eachpower stage and each function, the regulator controller should also haveaccess to the resistivity of the conduction path so that the overallresistance can be calculated. Alternatively, the regulator controller 38may directly identify the resistance between each power stage and eachfunction. For example, a designer may pre-program the regulatorcontroller with set values that represent the resistance (or thedistance and resistivity) between each power stage and each of thevarious circuit functions. However, since the resistance changes withdistance between a power stage and a function, much of the discussionherein is framed in terms of distance.

The IC controller 24 communicates with the regulator controller 38 overa control line or bus to identify an activity level of one or moreactive functions 22A-D on the integrated circuit 20. The activity levelmay be in units of electrical current or may be converted from otherunits, such as processor instructions, to an amount of electricalcurrent. Accordingly, the regulator controller 38 has informationidentifying the distances between each power stage and each function, aswell as the amount of current that needs to be supplied to each function22A-D. The regulator controller 38 may use this information to determinean amount of current that should be supplied by each of the regulatorphases in order to reduce or minimize the power losses associated withproviding the current requirements of each function. As a practicalmatter, the regulator controller will control the power stages so that agreater than equal amount of current is provided by a power stage thatis closest to the function with the highest activity level. In otherwords, the regulator controller may intentionally imbalance the amountof current provided by each regulator stage. As the activity level orload shifts among the functions (i.e., shifts among locations), thepower stages may be dynamically controlled in real time so that powerlosses are continually reduced or minimized.

The regulator controller may control the power stages to reduce orminimize power losses regardless of whether all of the functions areactive or only a subset of the functions are active (i.e., one or moreof the functions are OFF (i.e., consuming no power)). For the caseswhere only one function is active, the IC controller may communicatewith the regulator controller to identify which function (i.e., whichlocation, such as a quadrant) is active. With this information, theregulator may reduce current through, or perhaps shut off, those powerstages that are physically most distant from the active function andleave on the one or more phases that are physically closer to the activefunction. For example, if only one function is active and that onefunction is consuming 6 A, a traditional DC voltage regulator wouldcause each power stage to supply an equal amount of current to thatfunction (or 1 A per power stage). However, in accordance with methodsof the present invention, the regulator controller causes the powerstage closest to the load activity to supply a greater portion (or all)of the current to the active function. Power stages that are physicallyfurther from the active function will provide a lesser portion, if any,of the current to the active function.

FIG. 2 is a diagram of the system 10 illustrating current conductionspaths (see arrows) from each of the power stages 31-36 to an activefunction 22B (Function B) of the integrated circuit 20. The totalcurrent conduction path length for each power stage is a current loopfrom a particular power stage 31-36 to the active function 22B in thepower plane 12 and back to the particular power stage 31-36 in theground (GND) plane copper. In various embodiments of the presentinvention, the amount of current supplied to the active function isweighted to one or more power stages nearest to the active function sothat more of the current has a shorter conduction path length than powerstages that are further from the active function. In this example, alarger amount of current may be supplied by the closest power stages 32,33 (S2 and S3), a smaller amount of current may be supplied by the nextclosest power stages 31, 34 (S1 and S4), and an even smaller amount, ifany, current may be supplied by the furthest power stages 35, 36 (S5 andS6).

FIG. 3 is a diagram of the system 10 illustrating power losses whenproviding power to a single active function 22B from two power stages35, 36 (S5 and S6) that are on the furthest side of the integratedcircuit 20 from the active function 22B. Various details from FIGS. 1and 2 have been omitted from FIGS. 3-5 for the purpose of focusing onthis specific examples.

As shown in FIG. 3, only the one function 22B in the upper rightquadrant of the integrated circuit 20 is active, and that one function22B is requiring 2 A of electrical current. When the 2 A of current issupplied equally by the two power stages 35, 36 (S5 and S6), each powerstage supplies 1 A of current that must follow a long current pathlength through copper power and ground planes such that the electricalresistance is 4R in the power plane and 4R in the ground plane. Sincethe total power loss is equal to the sum of the individual power losses,the total power loss is Σ I²R, where I is the current and R is theelectrical resistance. Accordingly, the total power loss (ignoringunits) is Σ I²R=(1)²(4)+(1)²(4)+(1)²(4)+(1)²(4)=4+4+4+4=16.

FIG. 4 is a diagram of the system 10 illustrating power losses whenproviding the same requirement of 2 A current to the same activefunction 22B from two power stages 33, 36 (S3 and S6) on opposing sidesof the integrated circuit function. Since one power stage 33 (S3) isphysically located closer to the active function 22B, the current pathto and from the active function is much shorter than the current pathbetween the other power stage 36 (S6) and the active function. As aresult, the electrical resistance associated with the current path inthe power plane and in the ground plane when using the power stage 33(S3) is only 1R, as compared to an electrical resistance of 4R in thecurrent path associated with the other power stage 36 (S6). As shown inFIG. 4, the two power stages 33, 36 (S3 and S6) are both providing 1 Aof current to the active function. Accordingly, the total power loss(ignoring units) is Σ I²R=(1)²(4)+(1)²(4)+(1)²(1)+(1)²(1)=4+4+1+1=10.

FIG. 5 is a diagram of the system 10 illustrating power losses whenproviding power to the active function from the power stage that is thenearest to active function. As shown, the closest power stage 33 (S3) isproviding the entire 2 A of current required by the active function 22B.Accordingly, the total power loss (ignoring units) is ΣI²R=(0)²(0)+(0)²(0)+(2)²(1)+(2)²(1)=0+0+4+4=8. While the power lossassociated with supplying all of the current from the closest powerstage is less than the power losses shown in reference to either FIG. 3or FIG. 4, further optimization is certainly possible in accordance withthe methods of the present invention. For example, providing currentfrom the closest two power stages 32, 33 (S2 and S3) would likelyprovide even lower power losses than shown in reference to FIG. 5. Inanother example, it is likely that supplying some small fraction of thecurrent from other power stages would also provide even lower powerlosses. It should be recognized that any number of power stages maysupply current at the same time, and that any power stage could becontrolled to provide any weighted percentage of the total currentrequirement of the active function(s).

FIG. 6 is a flowchart of a method 40 according to one embodiment of thepresent invention. In step 42, the method obtains an activity level foreach of a plurality of functions of an integrated circuit, wherein eachfunction has a different physical location on the integrated circuit. Instep 44, the method dynamically adjusts an amount of current supplied tothe integrated circuit by each of a plurality of power stages of a DCvoltage regulator to meet the current requirements of the plurality offunctions and to control power losses between the power stages and thefunctions, wherein each power stage has a different physical locationalong a perimeter of the integrated circuit.

The present invention may be a system, a method, and/or a computerprogram product. The computer program product may include a computerreadable storage medium (or media) having computer readable programinstructions thereon for causing a processor to carry out aspects of thepresent invention.

The computer readable storage medium can be a tangible device that canretain and store instructions for use by an instruction executiondevice. The computer readable storage medium may be, for example, but isnot limited to, an electronic storage device, a magnetic storage device,an optical storage device, an electromagnetic storage device, asemiconductor storage device, or any suitable combination of theforegoing. A non-exhaustive list of more specific examples of thecomputer readable storage medium includes the following: a portablecomputer diskette, a hard disk, a random access memory (RAM), aread-only memory (ROM), an erasable programmable read-only memory (EPROMor Flash memory), a static random access memory (SRAM), a portablecompact disc read-only memory (CD-ROM), a digital versatile disk (DVD),a memory stick, a floppy disk, a mechanically encoded device such aspunch-cards or raised structures in a groove having instructionsrecorded thereon, and any suitable combination of the foregoing. Acomputer readable storage medium, as used herein, is not to be construedas being transitory signals per se, such as radio waves or other freelypropagating electromagnetic waves, electromagnetic waves propagatingthrough a waveguide or other transmission media (e.g., light pulsespassing through a fiber-optic cable), or electrical signals transmittedthrough a wire.

Computer readable program instructions described herein can bedownloaded to respective computing/processing devices from a computerreadable storage medium or to an external computer or external storagedevice via a network, for example, the Internet, a local area network, awide area network and/or a wireless network. The network may comprisecopper transmission cables, optical transmission fibers, wirelesstransmission, routers, firewalls, switches, gateway computers and/oredge servers. A network adapter card or network interface in eachcomputing/processing device receives computer readable programinstructions from the network and forwards the computer readable programinstructions for storage in a computer readable storage medium withinthe respective computing/processing device.

Computer readable program instructions for carrying out operations ofthe present invention may be assembler instructions,instruction-set-architecture (ISA) instructions, machine instructions,machine dependent instructions, microcode, firmware instructions,state-setting data, or either source code or object code written in anycombination of one or more programming languages, including an objectoriented programming language such as Smalltalk, C++ or the like, andconventional procedural programming languages, such as the “C”programming language or similar programming languages. The computerreadable program instructions may execute entirely on the user'scomputer, partly on the user's computer, as a stand-alone softwarepackage, partly on the user's computer and partly on a remote computeror entirely on the remote computer or server. In the latter scenario,the remote computer may be connected to the user's computer through anytype of network, including a local area network (LAN) or a wide areanetwork (WAN), or the connection may be made to an external computer(for example, through the Internet using an Internet Service Provider).In some embodiments, electronic circuitry including, for example,programmable logic circuitry, field-programmable gate arrays (FPGA), orprogrammable logic arrays (PLA) may execute the computer readableprogram instructions by utilizing state information of the computerreadable program instructions to personalize the electronic circuitry,in order to perform aspects of the present invention.

Aspects of the present invention are described herein with reference toflowchart illustrations and/or block diagrams of methods, apparatus(systems), and computer program products according to embodiments of theinvention. It will be understood that each block of the flowchartillustrations and/or block diagrams, and combinations of blocks in theflowchart illustrations and/or block diagrams, can be implemented bycomputer readable program instructions.

These computer readable program instructions may be provided to aprocessor of a general purpose computer, special purpose computer, orother programmable data processing apparatus to produce a machine, suchthat the instructions, which execute via the processor of the computeror other programmable data processing apparatus, create means forimplementing the functions/acts specified in the flowchart and/or blockdiagram block or blocks. These computer readable program instructionsmay also be stored in a computer readable storage medium that can directa computer, a programmable data processing apparatus, and/or otherdevices to function in a particular manner, such that the computerreadable storage medium having instructions stored therein comprises anarticle of manufacture including instructions which implement aspects ofthe function/act specified in the flowchart and/or block diagram blockor blocks.

The computer readable program instructions may also be loaded onto acomputer, other programmable data processing apparatus, or other deviceto cause a series of operational steps to be performed on the computer,other programmable apparatus or other device to produce a computerimplemented process, such that the instructions which execute on thecomputer, other programmable apparatus, or other device implement thefunctions/acts specified in the flowchart and/or block diagram block orblocks.

The flowchart and block diagrams in the Figures illustrate thearchitecture, functionality, and operation of possible implementationsof systems, methods, and computer program products according to variousembodiments of the present invention. In this regard, each block in theflowchart or block diagrams may represent a module, segment, or portionof instructions, which comprises one or more executable instructions forimplementing the specified logical function(s). In some alternativeimplementations, the functions noted in the block may occur out of theorder noted in the figures. For example, two blocks shown in successionmay, in fact, be executed substantially concurrently, or the blocks maysometimes be executed in the reverse order, depending upon thefunctionality involved. It will also be noted that each block of theblock diagrams and/or flowchart illustration, and combinations of blocksin the block diagrams and/or flowchart illustration, can be implementedby special purpose hardware-based systems that perform the specifiedfunctions or acts or carry out combinations of special purpose hardwareand computer instructions.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,components and/or groups, but do not preclude the presence or additionof one or more other features, integers, steps, operations, elements,components, and/or groups thereof. The terms “preferably,” “preferred,”“prefer,” “optionally,” “may,” and similar terms are used to indicatethat an item, condition or step being referred to is an optional (notrequired) feature of the invention.

The corresponding structures, materials, acts, and equivalents of allmeans or steps plus function elements in the claims below are intendedto include any structure, material, or act for performing the functionin combination with other claimed elements as specifically claimed. Thedescription of the present invention has been presented for purposes ofillustration and description, but it is not intended to be exhaustive orlimited to the invention in the form disclosed. Many modifications andvariations will be apparent to those of ordinary skill in the artwithout departing from the scope and spirit of the invention. Theembodiment was chosen and described in order to best explain theprinciples of the invention and the practical application, and to enableothers of ordinary skill in the art to understand the invention forvarious embodiments with various modifications as are suited to theparticular use contemplated.

What is claimed is:
 1. A method, comprising: obtaining an activity levelfor each of a plurality of functions of an integrated circuit, whereineach function has a different physical location on the integratedcircuit; and dynamically adjusting an amount of current supplied to theintegrated circuit by each of a plurality of power stages of a DCvoltage regulator to meet the current requirements of the plurality offunctions and to control power losses between the power stages and thefunctions, wherein each power stage has a different physical locationalong a perimeter of the integrated circuit.
 2. The method of claim 1,wherein the amount of current supplied by each power stage isdynamically adjusted to reduce power losses between the power stages andthe functions relative to an amount of power losses that would occur ifeach power stage provided an equal amount of current.
 3. The method ofclaim 1, wherein the amount of current supplied by each power stage isdynamically adjusted to minimize power losses between the power stagesand the functions.
 4. The method of claim 1, wherein the amount ofcurrent supplied by each power stage is weighted according to theactivity level of a function closest to each power stage.
 5. The methodof claim 1, wherein the integrated circuit is rectangular and theplurality of power stages are located on at least two opposing sides ofthe integrated circuit.
 6. The method of claim 5, wherein the pluralityof functions includes at least four functions and the plurality of powerstages includes at least four power stages.
 7. The method of claim 6,wherein at least one of the power stages is directly adjacent each oneof the functions.
 8. The method of claim 6, wherein the plurality ofpower stages includes six power stages distributed around the perimeterof the integrated circuit, wherein there are two power stages located oneach of three sides of the integrated circuit.
 9. The method of claim 1,wherein the activity level of each function is updated continuouslyduring operation of the integrated circuit.
 10. The method of claim 9,further comprising: an internal controller of the integrated circuitcommunicating the activity level to a regulator controller over acontrol line or bus, wherein the regulator controller controls each ofthe power stages.
 11. The method of claim 9, wherein the amount ofcurrent provided by each power stage is dynamically controlled inresponse to the updated activity level for each function.
 12. The methodof claim 1, wherein the plurality of functions are processor cores. 13.The method of claim 1, further comprising: calculating the power lossesbetween the power stages and the functions as the sum of the power lossbetween each power stage and each function, wherein the power loss is afunction of the square of the amount of current multiplied by theelectrical resistance in a conduction path from the power stage to thefunction.
 14. The method of claim 13, wherein the electrical resistancein the conduction path is a function of electrical resistivity of theconduction path and a path length of the conduction path.
 15. The methodof claim 14, further comprising: storing a known path length orelectrical resistance for each possible pairing of one of the functionsand one of the power stages.
 16. The method of claim 1, wherein theplurality of functions includes a first function having an activitylevel that is greater than an activity level of the other functions,wherein the plurality of power stages includes a first power stage thatis closest to the first function, and wherein the step of dynamicallyadjusting an amount of current provided to the integrated circuit byeach of a plurality of power stages of a DC voltage regulator includescausing the first power stage to supply a greater than equal portion ofthe amount of current provided to the integrated circuit.
 17. The methodof claim 1, further comprising: measuring the activity level of eachfunction of the integrated circuit by way of a counter, a task size, ora processor sleep state.
 18. The method of claim 1, further comprising:determining a future activity level of a function by analyzing a queueof pending workload.
 19. The method of claim 1, further comprising:accessing a fixed lookup table that identifies an amount of current foreach power stage for a particular activity level of each function. 20.The computer program product of claim 1, wherein each power stagesupplies electrical current to a power plane and each function iselectrically connected between the power plane and a ground plane, andwherein the power losses between the power stages and the functionsoccur in the power plane and the ground plane; the method furthercomprising: calculating the power losses in the power and ground planesas the sum of the power loss between each power stage and each function,wherein the power loss is a function of the square of the amount ofcurrent multiplied by the electrical resistance in a current loop fromthe power stage to the function through the power plane and from thefunction to the power stage through the ground plane.